The insulated-gate field-effect transistor (IGFET) has been arranged in various configurations of bistable stages, or cells, resembling bipolar transistor flip-flops. Unlike a conventional bipolar junction transistor, in which both majority and minority carriers are required for operation, an IGFET is a unipolar transistor to the extent that only majority carriers are required for operation. Conduction in an IGFET device is controlled by signals applied to a control electrode, without any current flow between the control electrode and controlled electrodes because the control electrode in insulated from the controlled electrodes. IGFET memory cells consume significantly less power than bipolar transistor cells.
Individual memory cells are addressed by data input and output lines, with each memory cell commonly having two output bit lines (e.g., a bit line BL and a complementary bit line/BL) for indicating the existence of a “0” or “1” bit stored in the memory cell. The “0” and “1” bits are represented by different voltages that are of small magnitude and are subject to errors over time that tend to reduce the difference between the respective voltages. Therefore, it is conventional practice to provide sense amplifiers connected to the output bit lines of a memory cell, which are adapted to accurately detect or “sense” the small voltage differences between the bit lines and to amplify such differences so as to latch the bit value indicated thereby to provide a more accurate read out.
A conventional sense amplifier includes cross-coupled field effect transistor pairs (FETs) each having a first current carrying electrode (source or drain electrode) coupled to a respective one of the bit lines via an input switch, and gate electrodes cross-coupled to each other and to respective output terminals of the sense amplifier circuit. A sense amplifier enabling (SAE) FET receives a control signal which permits or prevents turning ON of the transistors. The signal to be sensed appears on only one of the bit lines, which then carries a voltage higher or lower than the other bit line, depending on the value of the sensed signal. Consequently, when the control signal is applied to the connected SAE FET to permit turn ON of the two transistors, the transistor having its gate electrode coupled to the bit line carrying the higher voltage will turn ON first. The other transistor will thereafter be maintained in its off state to latch the information read out from the memory cell.
However, the sensitivity of such a sense amplifier depends critically on the threshold voltage Vth of each field effect transistor. If the threshold voltage of the transistor which is intended to turn ON first becomes significantly larger than the threshold voltage of the other transistor, the other transistor will turn ON instead of the first transistor, resulting in an erroneous read operation. The development of integration and miniaturization techniques has made the possible variation or divergence in threshold voltages among FETs correspondingly larger. The resulting increased possibility of sensing errors is a significant concern in the further optimization of memory array structures.
Silicon-on-insulator (SOI) technology has been used for the manufacture of FETs to improve (i.e., reduce) gate delay. As its name implies, SOI technology involves the formation of semiconductor devices in silicon layers that completely overlie an insulator layer. SOI technology has improved performance characteristics by reducing parasitic capacitances in semiconductor devices. As known in the art, because of the presence of an insulator layer on the surface of a semiconductor layer, body contacts are used to ground such FETs in order to avoid the so-called “history effect,” whereby SOI FETs receiving many logic ones over a period of time tend to become biased in a given direction and thus require a much longer time than typical or desired to react to a logic zero input because of the resulting mismatch in threshold voltage Vth.
FIG. 2 shows an example sense amplifier according to the conventional art. Cross-coupled transistor pairs 104–106 include P-channel FETs (field effect transistors) 104 and 105, and N-channel FETs 106 and 107, coupled in a CMOS (complementary metal oxide semiconductor) inverter fashion. FETs 104 and 105 each have their source terminal connected to a positive voltage designated as Vdd.
N-channel FETs 101 and 102 are input transistors for the sense amplifier. FET 101 receives at input terminal IN a voltage from a bit line of a memory storage cell. FET 102 receives at complementary input terminal /IN a voltage from a complementary bit line of the memory storage cell. N-channel FET 103 is shown having a SAE (Sense Amplifier Enable) signal supplied to a gate thereof.
As known to those skilled in the art, P-type FETs turn ON to allow current flow from source to drain when the gate terminal is at a low or negative potential with respect to the source. When the gate potential is positive or the same as the source, the P-type FET is OFF, and does not conduct current. On the other hand, N-type FETs turn ON to allow current flow from source to drain when the gate terminal is high or positive with respect to the source. When the gate potential is negative or the same as the source, the N-type FET is OFF, and does not conduct current.
Output terminal SAout is connected to the drain terminals of FETs 105 and 107, and to the gate terminals of FETs 104 and 106. Complementary output terminal /SAout is connected to the drain terminals of FETs 104 and 106, and to the gate terminals of FETs 105 and 107. Input FETs 101 and 102 have grounded body contacts 110.
In operation, the sense amplifier circuit as shown in FIG. 2 detects a voltage difference between signals inputted to input terminals IN and /IN from a corresponding bit line and complementary bit line as stored in a memory cell. When an enable signal is sent to sense amplifier enable terminal SAE, FET 103 is turned ON and couples the circuit to ground, such that current begins to flow through the FETs 101 and 102 connected to receive bit lines signals at gates IN and/IN. In the example where a logic “0” is read from a memory cell, gate IN will have a lower input voltage than gate /IN at the time SAE turns on FET 103. Thus, FET 101 initially will conduct less current than FET 102, and, as a result, FET 106 will not pull down terminal /SAout as much as FET 102 pulls down terminal SAout.
As a result, the voltage at node SAout will fall faster than that at node /SAout. As the voltage at SAout falls, it will begin to shut off FET 106, and thereby causing even more current to pull down the voltage at SAout. When FET 106 is OFF, FET 104 will turn ON and cause node /SAout to return to a high level. Thus, the sense amplifier depends upon the current regulation abilities of input signal FETs 101 and 102. As previously mentioned, to avoid a problem caused by the history effect where the body of the FET becomes biased in a given direction, body contacts 110 are provided to tie the body of the FETs 101 and 102 to ground.
However, the gate capacitance of a body-tied FET is much larger than that of a floating body FET. This larger capacitance results in an undesirably slow transition time. Consequently, there remains a need in the art for improvement in sense amplifier configurations to reduce or eliminate these shortcomings.